| 摘要 |
<P>PROBLEM TO BE SOLVED: To efficiently use cache memory when accessing to plural banks. <P>SOLUTION: A cache memory 120 holds data in a unit of entry held in a part of region of a memory 200 having plural banks. A bus master 110 issues one access address when requesting access to identical data held in the plural banks. With this issue, only one entry corresponding to each memory address in the plural banks that hold the identical data is registered in the cache memory 120. When the access address is issued from the bus master 110, the memory controller 130 identifies each memory address in the plural banks holding the identical data based on the access address, and accesses to one memory address in the identified memory addresses. <P>COPYRIGHT: (C)2012,JPO&INPIT |
