发明名称 TIME DIGITAL CONVERSION CIRCUIT AND CALIBRATION THEREFOR
摘要 <P>PROBLEM TO BE SOLVED: To reduce power consumption of a TDC circuit with high resolution. <P>SOLUTION: The TDC according to the present invention includes: a ring oscillator 10 having a delay line with a plurality of delay elements 11 for delaying an input signal connected in series, an inversion element 13 for outputting an inversion signal of an output of the delay element at the last stage of the delay line and a multiplexer 15 that provides any of output signals of a reference clock or the inversion element to the delay element at a first stage of the delay line; a plurality of determination circuits 17 which are connected to connection nodes of the delay elements of the delay line or input nodes of the delay elements at the first stage and which determines whether a change edge of a signal to be measured advances or delays against a change edge of a delayed signal of the reference clock output by the delay element 11; an encode circuit 31 that encodes a determination result of the determination circuit 17; and a calculation circuit 33 that calculates a phase to the reference clock of the change edge of the signal to be measured from an output of the encoder circuit 31. <P>COPYRIGHT: (C)2012,JPO&INPIT
申请公布号 JP2011259208(A) 申请公布日期 2011.12.22
申请号 JP20100131923 申请日期 2010.06.09
申请人 HANDOTAI RIKOUGAKU KENKYU CENTER:KK 发明人 ITO SATOSHI;KOBAYASHI HARUO
分类号 H03K21/02;G01R31/319;H03K21/38;H03K21/40;H03L7/06;H03M1/10;H03M1/50 主分类号 H03K21/02
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