| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide an interface circuit that detects a phase relation between data and a clock during a memory access operation without decreasing the performance of a system. <P>SOLUTION: A first delay circuit 110 gradually delays a clock signal CLK and generates a first delay signal CLK1, a second delay signal CLK2 having a phase faster than the first delay signal CLK1 by a predetermined value, and a third delay signal CLK3 having a phase slower than the first delay signal CLK1 by a predetermined value. The fist delay circuit has a delay amount that is set so that the edge of the first delay signal CLK1 corresponds to the center part of a unit data of data signal DQ when the data signal DQ and the clock signal CLK have a predetermined phase relation. A data retrieval part 120 retrieves data from the data signal DQ based on the first to third delay signals to obtain a respective first to third data. An output circuit 130 outputs the first data to the outside of the circuit. A comparison part 140 makes a comparison among the first to third data. <P>COPYRIGHT: (C)2012,JPO&INPIT |
