| 发明名称 |
Implementation of wide multiplexers in reconfigurable logic |
| 摘要 |
A reconfigurable processing device comprises one or more reconfigurable processing units. At least one processing unit utilizes a computational unit having a preprocessing module for receiving n input signals, and s1 selection signals, and providing k output signals wherein k<n+s1. The computational unit further comprises an m-output look-up table being addressed by the k output signals of the preprocessing module and an output multiplexer for selecting one of the m output signals of the look-up table under control of s2 further selection signals. |
| 申请公布号 |
US8082284(B2) |
申请公布日期 |
2011.12.20 |
| 申请号 |
US20050507807 |
申请日期 |
2005.05.09 |
| 申请人 |
LEIJTEN-NOWAK KATARZYNA;ST-ERICSSON SA |
发明人 |
LEIJTEN-NOWAK KATARZYNA |
| 分类号 |
G06F7/38;H03K19/173;H03K19/177 |
主分类号 |
G06F7/38 |
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