发明名称 Two bits per cell non-volatile memory architecture
摘要 A memory circuit for holding a single binary value. A first bit cell holds one of a logical high value and a logical low value, and a second bit cell also holds one of a logical high value and a logical low value. Circuitry is provided for placing a logical high value in the first bit cell when the binary value in the memory circuit is to be a logical high value, and circuitry is provided for placing a logical high value in the second bit cell when the binary value in the memory circuit is to be a logical low value. In this manner, a logical high value exists within the memory circuit, whether the single binary value within the memory circuit is a logical high value or a logical low value. The difference between the two values of the binary value is which of the two bit cells holds the logical high value. Thus, this memory circuit can be sensed without the use of a sense amplifier.
申请公布号 US8081521(B2) 申请公布日期 2011.12.20
申请号 US20090370718 申请日期 2009.02.13
申请人 CHUA CHEE T.;RAO KAMESWARA K.;RAO VITHAL R.;CHEN JAWJI;YU DA-GUANG;RUETZ J. ERIC;FUNG STEPHEN;MOSYS, INC. 发明人 CHUA CHEE T.;RAO KAMESWARA K.;RAO VITHAL R.;CHEN JAWJI;YU DA-GUANG;RUETZ J. ERIC;FUNG STEPHEN
分类号 G11C7/00 主分类号 G11C7/00
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