发明名称 |
Enhanced microprocessor interconnect with bit shadowing |
摘要 |
Shadow selection logic is used to select a driver bit position as a shadowed driver value, and line drivers to transmit data for the selected driver bit position and the shadowed driver value on separate link segments of a bus. In addition shadow compare logic is used to compare a selected received value with a shadowed received value from the bus and identify a miscompare in response to a mismatch of the compare, and shadow counters to count a rate of the miscompare relative to a bus error rate over a period of time. A defective link segment is identified in response to the rate of the miscompare within a predefined threshold of the bus error rate. |
申请公布号 |
US8082475(B2) |
申请公布日期 |
2011.12.20 |
申请号 |
US20080165848 |
申请日期 |
2008.07.01 |
申请人 |
FERRAIOLO FRANK D.;DREPS DANIEL M.;GOWER KEVIN C.;REESE ROBERT J.;INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
FERRAIOLO FRANK D.;DREPS DANIEL M.;GOWER KEVIN C.;REESE ROBERT J. |
分类号 |
G06F11/14;G06F11/30 |
主分类号 |
G06F11/14 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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