| 摘要 |
PURPOSE: A data input circuit is provided to sufficiently secure margin outputted from a transmission unit by outputting the first to fourth input data of a data latch unit as a signal with a pulse width corresponding to two cycle section of an inner clock. CONSTITUTION: A clock sampling unit(30) generates a shifting signal with a pulse generated after a write latency elapses and generates a sampling clock by sampling the inner clock for a burst section from a pulse generation point of a shifting signal. A final clock generator(31) generates a level signal by latching and synchronizing the shifting signal with the sampling clock and generates the final clock from a level signal in response to the burst signal. A write latch signal generating unit(32) generates an enable signal by latching the final clock and generates a write latch signal in response to the enable signal.
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