发明名称 CMOS ANALOG SWITCH CIRCUIT AND NEGATIVE VOLTAGE SAMPLING CIRCUIT
摘要 <P>PROBLEM TO BE SOLVED: To provide a CMOS analog switch circuit allowing, in a low conduction state of an on-resistance, large signal input oscillating between a positive voltage side and a negative voltage side relative to a ground voltage. <P>SOLUTION: A CMOS analog switch circuit 103 with a complementary structure is configured to connect sources of a PMOS transistor 101 and an NMOS transistor 102 mutually to an input terminal 106, and connect drains of those mutually to an output terminal 107. The circuit is configured to supply a positive power supply voltage to a back gate of the PMOS transistor 101, supply a negative power supply voltage to a back gate of the NMOS transistor 102, supply any one of the positive power supply voltage and the negative power supply voltage to a gate of the PMOS transistor as a negative voltage control signal S1, and supply the other to a gate of the NMOS transistor as a negative voltage control signal S2. <P>COPYRIGHT: (C)2012,JPO&INPIT
申请公布号 JP2011254304(A) 申请公布日期 2011.12.15
申请号 JP20100126923 申请日期 2010.06.02
申请人 ASAHI KASEI ELECTRONICS CO LTD 发明人 INADA NORICHIKA
分类号 H03K17/687 主分类号 H03K17/687
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