发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 <P>PROBLEM TO BE SOLVED: To detect a process state of a semiconductor chip connected outside a semiconductor integrated circuit and to increase a margin of a set-up time or hold time of a control signal with respect to a mask cancellation signal. <P>SOLUTION: During a monitor mode, reference potential lower than normal is supplied to a reception circuit to determine a logical level of a transmission signal, so that the process state of the semiconductor chip connected outside the semiconductor integrated circuit is detected. In accordance with the detected process state, a variable delay circuit is controlled and a delay time of at least either an internal synchronizing signal or an external synchronizing signal is regulated. Thus, the set-up time or hold time of the control signal from the semiconductor chip with respect to the mask cancellation signal generated in response to the internal synchronizing signal is stabilized regardless of the process state of the semiconductor chip. <P>COPYRIGHT: (C)2012,JPO&INPIT
申请公布号 JP2011253412(A) 申请公布日期 2011.12.15
申请号 JP20100127652 申请日期 2010.06.03
申请人 FUJITSU SEMICONDUCTOR LTD 发明人 ANDOU NARIYOSHI
分类号 G06F12/00;G11C11/401;G11C11/407;H01L21/822;H01L27/04;H03K5/13;H03L7/00 主分类号 G06F12/00
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