CIRCUIT SYNTHESIZING DEVICE, METHOD, AND PROGRAM

摘要

In order for the disclosed circuit synthesizing device, etc. to reduce the number of operation synthesis execution cycles and reduce circuit lag, an operation synthesis device is used that is provided with: an operation synthesis means for converting the operation of a circuit device from a described operation level circuit description to a resistor transfer level description; a logical synthesis means that generates a netlist from the aforementioned resistor transfer level description; a disposition means that disposes the circuits described by the aforementioned netlist; a wiring means that wires between the aforementioned circuits; and a feedback means that extracts wiring lag for each state of the aforementioned operation synthesis means from the results of the aforementioned wiring, and inputs the lag to the aforementioned operation synthesis means. By means of operation synthesis that matches a wiring lag estimated from the disposition results or the actual wiring lag that is not a wiring lag assumed by an operation synthesis unit, the time until the circuit is synthesized is reduced.