发明名称 METHOD FOR SHIELDING MAIN BIT LINE FOR REFERENCE CELL
摘要 <p>A dummy main bit line (MBLD1) is arranged between a reference main bit line (MBLR1) and a core main bit line group (MBL1 to MBLj). A selection transistor (SLD1) provided between a sub bit line (BLD1) connected to a cell (31), and the main bit line (MBLD1) can be switched between a conductive state and a non-conductive state, independently from other selection transistors. The dummy main bit line (MBLD1) can be set to a ground potential by a shield grounding means (DTD1, 106) and can be used as a shield line for the reference main bit line (MBLR1).</p>
申请公布号 WO2011155120(A1) 申请公布日期 2011.12.15
申请号 WO2011JP02633 申请日期 2011.05.11
申请人 PANASONIC CORPORATION;UEDA, TAKANORI;NAKAYAMA, MASAYOSHI;KOUNO, KAZUYUKI 发明人 UEDA, TAKANORI;NAKAYAMA, MASAYOSHI;KOUNO, KAZUYUKI
分类号 G11C16/06;G11C16/04 主分类号 G11C16/06
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