发明名称
摘要 A multilevel interconnect structure in a semiconductor device and methods for fabricating the same are described. The multilevel interconnect structure in the semiconductor device includes a first insulating layer formed on a semiconductor wafer, a Cu interconnect layer formed on the first insulating layer, a second insulating layer formed on the Cu interconnect layer, and a metal oxide layer formed at an interface between the Cu interconnect layer and the second insulating layer. The metal oxide layer is formed by immersion-plating a metal, such as Sn or Zn, on the Cu interconnect layer and then heat-treating the plated layer in an oxidizing atmosphere.
申请公布号 JP4836092(B2) 申请公布日期 2011.12.14
申请号 JP20080071835 申请日期 2008.03.19
申请人 发明人
分类号 H01L21/3205;H01L21/768 主分类号 H01L21/3205
代理机构 代理人
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