VOLTAGE CONTROLLED DELAY LINE AND DELAY LOCKED LOOP CIRCUIT AND MULTI-PHASE CLOCK GENERATOR USING THE VOLTAGE CONTROLLED DELAY LINE

摘要

PURPOSE: A voltage control delay line, a delay locked loop circuit including the same, and a multi-phase clock generator are provided to stably operate in an initial process by equalizing delay properties between a plurality of clocks signals. CONSTITUTION: A voltage control delay line(120) operates in response to a lock signal and a voltage control signal and generates a plurality of clock signals which successively delay an input clock signal using a unit delay block. A phase frequency detection circuit generates an up signal and a down signal by using a clock signal with the fastest phase and a clock signal with the lowest phase. A charge pump/loop filter(140) generates a voltage control signal in response to the up signal and the down signal. A lock detection circuit(150) generates a lock signal in response to the up signal and the down signal.