发明名称 |
Microprocessor with improved data stream prefetching |
摘要 |
A microprocessor coupled to a system memory by a bus includes an instruction decode unit that decodes an instruction that specifies a data stream in the system memory and a stream prefetch priority. The microprocessor also includes a load/store unit that generates load/store requests to transfer data between the system memory and the microprocessor. The microprocessor also includes a stream prefetch unit that generates a plurality of prefetch requests to prefetch the data stream from the system memory into the microprocessor. The prefetch requests specify the stream prefetch priority. The microprocessor also includes a bus interface unit (BIU) that generates transaction requests on the bus to transfer data between the system memory and the microprocessor in response to the load/store requests and the prefetch requests. The BIU prioritizes the bus transaction requests for the prefetch requests relative to the bus transaction requests for the load/store requests based on the stream prefetch priority. |
申请公布号 |
US8078806(B2) |
申请公布日期 |
2011.12.13 |
申请号 |
US20100911392 |
申请日期 |
2010.10.25 |
申请人 |
DIEFENDORFF KEITH E.;MIPS TECHNOLOGIES, INC. |
发明人 |
DIEFENDORFF KEITH E. |
分类号 |
G06F12/00;G06F12/08 |
主分类号 |
G06F12/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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