Low power SSTL memory controller

摘要

An integrated circuit device having configurable resources is configured as a memory controller that includes a plurality of bi-directional pins, an input buffer circuit that is operable to receive SSTL-compliant input and an output buffer that is operable to generate SSTL-compliant output. The input buffer circuit includes a first single-ended buffer coupled to a first voltage source and to a ground voltage. The first single-ended buffer has an input coupled to one of the bi-directional pins and has an output coupled to the control logic of the memory controller.