| 摘要 |
Decoder for low-density parity check convolutional codes. In at least some embodiments, a decoder (200) for arbitrary length blocks of low-density, parity-check codes includes a plurality of interconnected processors (202), which further include a plurality of interconnected nodes. A memory can be interconnected with the nodes to store intermediate log likelihood ratio (LLR) values based on channel LLR values. Thus, LLR values having successively improved accuracy relative to the channel LLR values can be output from each processor, and eventually used to decision information bits. In some embodiments, the memory is a random access memory (RAM) device that is adapted to store the intermediate LLR values in a circular buffer. Additionally, a storage device such as a read-only memory (ROM) device can be used to generate a predetermined plurality of addresses for reading and writing LLR values. |
