发明名称 |
Method and device for three-dimensional path planning to avoid obstacles using multiple planes |
摘要 |
An obstacle-avoidance-processor chip for three-dimensional path planning comprises an analog processing circuit and at least two analog-resistive-grid networks. The analog processing circuit is communicatively coupled to receive data from an inertial measurement unit and from at least one obstacle-detection sensor. The analog processing circuit is configured to construct a three-dimensional obstacle map of an environment based on the received data. The at least two analog-resistive-grid networks are configured to map obstacles in at least two respective non-parallel planes in the constructed three-dimensional obstacle map. The at least two analog-resistive-grid networks form a quasi-three-dimensional representation of the environment. The obstacle-avoidance-processor chip generates information indicative of a three-dimensional unobstructed path in the environment based on the obstacle maps. |
申请公布号 |
US8078399(B2) |
申请公布日期 |
2011.12.13 |
申请号 |
US20080045449 |
申请日期 |
2008.03.10 |
申请人 |
ARIYUR KARTIK B.;LAUTENSCHLAGER ERIC;ELGERSMA MICHAEL R.;HONEYWELL INTERNATIONAL INC. |
发明人 |
ARIYUR KARTIK B.;LAUTENSCHLAGER ERIC;ELGERSMA MICHAEL R. |
分类号 |
G01C21/00 |
主分类号 |
G01C21/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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