| 摘要 |
One embodiment is an information processing device for obtaining an HMAC, including a padding circuit for generating first key data by adding a first constant with respect to secret key data when a secret key length of input secret key data is shorter than a block length of a hash function, setting the secret key data as second key data when the secret key length is equal to the block length, generating third key data by adding the first constant with respect to a first digest value when the secret key length is longer than the block length, and performing an exclusive OR operation with a second constant with respect to one of the first key data, the second key data, or the third key data to calculate first data; a hash calculation circuit for obtaining the first digest value and obtaining a second digest value; and a control unit for managing a processing state for calculating the HMAC, wherein the hash calculation circuit outputs a first midway progress value when interrupting a calculation process of the first digest value in the middle, and resumes the calculation process of the first digest using the first midway progress value when a signal indicating resuming instruction of the calculation process of the first digest value is input to the control unit. |
