发明名称 SEMICONDUCTOR WAFER PATTERN EXPOSURE METHOD
摘要 <P>PROBLEM TO BE SOLVED: To provide a semiconductor wafer pattern exposure method capable of increasing the number of chips obtainable from a semiconductor wafer. <P>SOLUTION: A semiconductor wafer pattern exposure method is such that, when a circuit pattern is exposed to a semiconductor wafer 18 while sequentially moving a rectangle-shaped exposure unit area 35 in a first direction parallel to the short sides of the rectangle, the semiconductor wafer 18 is tilted during exposure so that the surface roughness in the exposure unit area 35 due to an uneven thickness of the semiconductor wafer 18 will become smaller on a focal plane of exposure. In the above method, an edge exclusion area 31 of the semiconductor wafer 18 defined for excluding the peripheral section thereof from the areas for which exposure or the focal plane of exposure is determined, is set in such a way that a first exclusion width d1 in the first direction is smaller than a second exclusion width d2 in a second direction at right angles to the first direction. And, within the exposure unit area 35 not including the edge exclusion area 31, the focal plane of exposure is set by tilting the semiconductor wafer 18 so that the surface roughness becomes smaller on the focal plane of exposure. <P>COPYRIGHT: (C)2012,JPO&INPIT
申请公布号 JP2011249627(A) 申请公布日期 2011.12.08
申请号 JP20100122265 申请日期 2010.05.28
申请人 TOSHIBA CORP 发明人 UDO YUSUKE;NITTA SHINICHI;SUZUKI MASARU
分类号 H01L21/027 主分类号 H01L21/027
代理机构 代理人
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