发明名称 METHODS FOR FORMING A GATE AND A SHALLOW TRENCH ISOLATION REGION AND FOR PLANARIZING AN ETCHED SURFACE OF SILICON SUBSTRATE
摘要 A method for forming a gate, which can improve the etching uniformity of the sidewalls of the gate, includes the following steps: forming a dielectric layer on a semiconductor substrate; forming a polysilicon layer on the dielectric layer; etching the polysilicon layer; performing an isotropic plasma etching process on the etched polysilicon layer by using a mixed gases containing a fluorine-based gas and oxygen gas; and cleaning the semiconductor substrate subjected to the isotropic plasma etching process, thereby forming a gate. The present invention further provides a method for forming a shallow trench isolation region, which can improve the filling quality of a subsequent spacer and the electrical properties of the resultant shallow trench isolation region, and a method for planarizing an etched surface of silicon substrate, which can improve the etching uniformity of the surface of silicon substrate.
申请公布号 US2011300688(A1) 申请公布日期 2011.12.08
申请号 US201113208892 申请日期 2011.08.12
申请人 HAN QIUHUA;ZHANG HAIYANG;MA QINGTIAN;SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION 发明人 HAN QIUHUA;ZHANG HAIYANG;MA QINGTIAN
分类号 H01L21/762 主分类号 H01L21/762
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