发明名称 |
TIME-SHARED LATENCY LOCKED LOOP CIRCUIT FOR DRIVING A BUFFER CIRCUIT |
摘要 |
In an embodiment, a device includes a buffer circuit with first and second buffer outputs and a latency locked loop (LLL) circuit. The LLL circuit includes first and second LLL inputs for receiving first and second input signals and includes at least one shared component that is time shared. The at least one shared component is configured to measure edge timing errors in output signals on the first and second buffer outputs relative to the first and second inputs signals and to generate delay adjustment signals to adjust timing of edge transitions within the first and second input signals provided to the buffer circuit to control a total propagation delay from the first and second LLL inputs to the first and second buffer outputs.
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申请公布号 |
US2011298509(A1) |
申请公布日期 |
2011.12.08 |
申请号 |
US20100795612 |
申请日期 |
2010.06.07 |
申请人 |
KHOURY JOHN M.;VIEGAS EDUARDO;SILICON LABORATORIES, INC. |
发明人 |
KHOURY JOHN M.;VIEGAS EDUARDO |
分类号 |
H03L7/06 |
主分类号 |
H03L7/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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