| 摘要 |
Circuits for performing motion estimation (ME) and motion compensation (MC) are disclosed. In the ME circuit, rows of a first register are correspondingly coupled to rows of a first memory that stores a search range of a first frame, and rows of a second register are correspondingly coupled to rows of a second memory that stores a search range of a second frame. Block-matching metric calculations are performed through the search range to obtain a motion vector (MV). In the MC circuit, first multiplexers couples each row of a first register to corresponding row of a first memory, and each macro block (MB) may accordingly be selected from the first memory and loaded into the first register. Second multiplexers couples each row of a second register to corresponding row of a second memory, and each MB may accordingly be selected from the second memory and loaded into the second register.
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