发明名称 |
CIRCUIT FOR CLOCKING AN FPGA |
摘要 |
A circuit 1 comprises: an FPGA 2, which has an FLL circuit 5; a reference clock generator 4 of a first frequency or a reference clock input for receiving a reference clock of the first frequency; a programmable oscillator 3, which outputs a clock signal for the FPGA 2, wherein the FLL circuit 5 is designed to detect a first number of clock signals of the programmable oscillator 4 during a second number of periods of the reference clock, wherein the first number is greater than the second number, and to output a feedback signal in order to control the ratio between the first number and the second number by virtue of the feedback signal acting on the frequency of the programmable oscillator. |
申请公布号 |
WO2011151103(A1) |
申请公布日期 |
2011.12.08 |
申请号 |
WO2011EP55947 |
申请日期 |
2011.04.14 |
申请人 |
ENDRESS+HAUSER GMBH+CO.KG;SCHLACHTER, MARC;GIRARDEY, ROMUALD |
发明人 |
SCHLACHTER, MARC;GIRARDEY, ROMUALD |
分类号 |
H03K19/177;H03L7/181 |
主分类号 |
H03K19/177 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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