发明名称 |
METHOD FOR MANUFACTURING INTEGRATED CIRCUIT, AND SEMICONDUCTOR INTEGRATED CIRCUIT |
摘要 |
<p>Disclosed is a method for manufacturing a semiconductor integrated circuit wherein, in a layout design, if, after the establishment of a floor plan of the circuit including function blocks and IO blocks (external terminal I/F circuits), it is found that the length of a wire connecting an external terminal and an IO block corresponding to the external terminal increases, then the corresponding IO block is rearranged so as to be in the vicinity of an IO terminal, thereby relaxing constraints on the wire between the external IO block and the external terminal, and a timing adjusting device(s) corresponding to the length of the wire of a bus (or a shared bus) connecting a data transmission circuit and the external IO block is (are) inserted in the bus.</p> |
申请公布号 |
WO2011152013(A1) |
申请公布日期 |
2011.12.08 |
申请号 |
WO2011JP02985 |
申请日期 |
2011.05.27 |
申请人 |
PANASONIC CORPORATION;IWAHASHI, DAISUKE;TOJIMA, MASAYOSHI;KIYOHARA, TOKUZO |
发明人 |
IWAHASHI, DAISUKE;TOJIMA, MASAYOSHI;KIYOHARA, TOKUZO |
分类号 |
G06F17/50;H01L21/82;H01L21/822;H01L27/04;H03K19/00 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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