| 摘要 |
Apparatuses and methods for well buffering are disclosed. In one embodiment, an apparatus includes a complimentary metal oxide semiconductor (CMOS) switch having a gate, a drain, a source, and a well. The source and drain are formed in the well, and the gate is formed adjacent the well between the source and drain. The source is configured to receive a bias voltage from a power amplifier. The apparatus further includes a gate bias control block for biasing the gate voltage of the switch, a well bias control block for biasing the well voltage of the switch, and a buffer circuit for increasing the impedance between the well bias control block and the well of the switch.
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