| 摘要 |
PURPOSE: A clock generating circuit and a delay locked loop using the same are provided to use an external clock signal of a high frequency, thereby generating a stable DLL clock signal. CONSTITUTION: A plurality of variable delay units(111~114) outputs a plurality of delay clock signals by adjusting a delay amount of input clock signals by control of an allocated control signal. A phase comparing unit(120,220) compares the phases of the input clock signals, a reference clock signal, and a delay clock signal. A delay control unit(130) generates a plurality of delay control signals based on the comparison result. The delay control signals have different voltage levels according to the comparison result.
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