| 摘要 |
The present invention provides an architecture for a platform, which includes (1) gates located in a central area of a die for supporting an application layer; (2) a SerDes region located at one side of the die for holding at least one SerDes device; (3) a Link Layer Controller region, located adjacent the SerDes region and between the SerDes region and the gates, for supporting the at least one SerDes device; and (4) at least one RAM array for supporting the at least one SerDes device, the at least one RAM array being located at least one of adjacent the gates or between the gates and the Link Layer Controller region. |
