| 摘要 |
A plurality of processors in a multiprocessor circuit is electrically connected to a plurality of independently addressable memory banks via a connection circuit. The connection circuit is arranged to forward addresses from a combination of the processors to addressing inputs of memory banks selected by the addresses. The connection circuit provides for a conflict resolution scheme wherein at least one of the processors is associated with one of the memory banks as an associated processor. The connection circuit guarantees the associated processor a higher minimum guaranteed access frequency to the associated memory banks than to non-associated memory banks. A defragmenter detects data associated with a task running on the associated processor that is stored on one of the memory banks and moves the data to the associated memory banks during execution of the task. |
