发明名称 |
Memory employing redundant cell array of multi-bit cells |
摘要 |
A memory that employs a redundant cell array for recovery of one or more failed core cell arrays of multi-bit memory cells is described. The memory includes a plurality of core cell arrays, at least one redundant cell array, and a memory controller. The memory controller is configured to dynamically assign the redundant cell array to a failed core cell array when erasing at least a portion of the plurality of core cell arrays. The memory controller is further configured to provide read/write access to the redundant cell array when the failed core cell array is selected for read/write access. |
申请公布号 |
US8072802(B2) |
申请公布日期 |
2011.12.06 |
申请号 |
US20080329475 |
申请日期 |
2008.12.05 |
申请人 |
KIKUCHI KEIICHIRO;YAMAKI NORIHIKO;WADA HIROAKI;SPANSION LLC |
发明人 |
KIKUCHI KEIICHIRO;YAMAKI NORIHIKO;WADA HIROAKI |
分类号 |
G11C16/04 |
主分类号 |
G11C16/04 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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