发明名称 |
Method and apparatus for detecting clock gating opportunities in a pipelined electronic circuit design |
摘要 |
A pipeline electronic circuit and design methodology enables power conservation in the stages of the pipeline via a simulation that identifies clock-gating opportunities among the stages of the pipeline. In one embodiment, simulation results assist a designer in the design of the pipeline electronic circuit to achieve power conservation by incorporating clock-gating circuitry among the stages of the pipeline at clock gating opportunity locations that the simulation identifies.
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申请公布号 |
US8073669(B2) |
申请公布日期 |
2011.12.06 |
申请号 |
US20070842491 |
申请日期 |
2007.08.21 |
申请人 |
FERNSLER MATTHEW EARL;JACOBSON HANS MIKAEL;SROUJI JOHNY;SWANSON TODD;INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
FERNSLER MATTHEW EARL;JACOBSON HANS MIKAEL;SROUJI JOHNY;SWANSON TODD |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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