摘要 |
A circuit (10, 90, 100) and method (70) has a processing unit (28), a master clock generator (12) for providing a master clock and a plurality of phase-locked loops (14, 16, 18), each providing a respective clock signal. A plurality of dynamically variable delay circuits (30, 32, 34) each has a plurality of predetermined delay amounts. Clocked circuits (20, 22, 24) are coupled to respective clock signals provided by respective phase-locked loops. A performance detector (102) is coupled to receive the clock signals for determining a center of a quiet zone for at least one of the plurality of phase-locked loops (82). The phase-locked loops are turned off and on (86) and a respective one of the plurality of dynamically variable delay circuits is set to have a new predetermined value of delay which adjusts an edge of the master clock to a location that permits the data processing system to operate near substantially the center of the quiet zone (82, 84). |
申请人 |
FREESCALE SEMICONDUCTOR, INC.;STEPHENS, SAMUEL G.;BURCH, KENNETH R. |
发明人 |
STEPHENS, SAMUEL G.;BURCH, KENNETH R. |