| 摘要 |
<p>Provided is an access control circuit (20), wherein a memory accessing source (3) views a plurality of memory circuits (DIMM0, DIMM1) as one memory circuit, transmits a row address and a column address in time division, and specifies one memory circuit among a plurality of memory circuits with the column address. The access control circuit (20) conducts speculative accessing to a plurality of memory circuits upon receiving the row address, conducts accessing to just the specified memory circuit after receiving the column address, and sends a settling command for the speculative accessing to memory circuits that did not become the subject of the access. Or, in the case of a read access, the access control circuit (20) receives read-data of the specified memory circuit, and discards read-data received from memory circuits that did not become the subject of the access. This makes latency upon memory accessing smaller.</p> |
