发明名称 PHASE INTERPOLATOR, RECEPTION CIRCUITRY AND INFORMATION PROCESSING DEVICE
摘要 <p>Disclosed is a phase interpolator which has a configuration (DL1, Cp1, R1, Iv1, Pas1, SW2, Ci, A4, and ST1) for combining cyclic signals (SOA, SXOA, SOB, AND SXOB) which differ from one another in phase and amplitude to acquire cyclic signals (SO and SXO), and with a timing corresponding to the phase of the signal acquired by delaying a cyclic signal (SA) to be used in the combination, repeatedly detecting a value of the cyclic signal which has been combined while varying the amount of delay, comparing the detected values with one another, acquiring an amount of delay for which the detected value is determined to be maximal or minimal, acquiring a value of a cyclic signal which has been combined at a timing corresponding to the phase of the signal acquired by delaying the cyclic signal to be used in combination by the amount of the delay acquired, and adjusting the acquired value so as to fit within a predetermined range.</p>
申请公布号 WO2011148467(A1) 申请公布日期 2011.12.01
申请号 WO2010JP58841 申请日期 2010.05.25
申请人 FUJITSU LIMITED;NISHIYAMA, RYUICHI 发明人 NISHIYAMA, RYUICHI
分类号 H03L7/00 主分类号 H03L7/00
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