发明名称 Integrated circuit with timing adjustment mechanism
摘要 An integrated circuit 2 includes processing circuitry that includes a plurality of critical path circuits 4, 6, 8, 10. These critical path circuits include variable delay circuits 16 which add an additional delay in to the path delay through the critical paths so as to adjust the path delay to match a target path delay. Variable delay circuit 18 includes a tank capacitor 22 which is charged or discharged to generate a control voltage. This control voltage serves to control a power supply voltage fed to an inverter chain 28. Variation in the power supply voltage of the inverter chain 28 adjust the propagation speed of a processing signal through the inverter chain 28 and accordingly adjusts the additional delay imposed by the variable delay circuit.
申请公布号 US2011291731(A1) 申请公布日期 2011.12.01
申请号 US201113067249 申请日期 2011.05.18
申请人 JAVERLIAC VIRGILE;ARM LIMITED 发明人 JAVERLIAC VIRGILE
分类号 H03H11/26 主分类号 H03H11/26
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