| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a semiconductor device that has a sufficient latch-up resistance quantity, and a method of manufacturing the same. <P>SOLUTION: The semiconductor device has an N<SP POS="POST">+</SP>buffer layer (first semiconductor region) 11, an N-type drift layer (second semiconductor region) 12 provided on a main surface 11a, a drain electrode (first main electrode) 1 provided on the side of a main surface 11b, a P-type base layer (third semiconductor region) 13 provided on a main surface 12a, an N<SP POS="POST">+</SP>source layer (fourth semiconductor region) 14 provided to the P-type base layer 13, a source electrode (second main electrode) 2 provided in contact with the p-type base layer 13 and N<SP POS="POST">+</SP>source layer 14, a gate electrode (control electrode) 3 provided via a gate insulating film 31, a high-concentration N-type buried layer (fifth semiconductor region) 15 provided penetrating a center part of the N<SP POS="POST">+</SP>source layer 14, and a P<SP POS="POST">+</SP>carrier extraction layer (sixth semiconductor region) 16 provided to the P-type base layer 13 in contact with a bottom part of the N<SP POS="POST">+</SP>source layer 14 and having higher impurity density than the P-type base layer 13. <P>COPYRIGHT: (C)2012,JPO&INPIT |
