发明名称 CLOCK GENERATION CIRCUIT
摘要 <P>PROBLEM TO BE SOLVED: To provide a clock generation circuit capable of making a lock-up time short. <P>SOLUTION: The clock generation circuit 1 comprises: a spread spectrum clock generation circuit 10 generating a modulation clock SCLK with a frequency modulated based on a reference clock RCLK; and a phase comparator 20 that outputs a H level lock signal LOCK when detecting phase coincidence between the reference clock RCLK and the modulation clock SCLK. Moreover, the clock generation circuit 1 comprises a selector 50 that selects the reference clock RCLK as an output clock CLK until the H level lock signal LOCK is output, and selects the modulation clock SCLK in response to the output of the H level lock signal. <P>COPYRIGHT: (C)2012,JPO&INPIT
申请公布号 JP2011244128(A) 申请公布日期 2011.12.01
申请号 JP20100113123 申请日期 2010.05.17
申请人 FUJITSU SEMICONDUCTOR LTD 发明人 SHIMIZU TAKASHI
分类号 H03L7/08;G06F1/08;H03K5/26;H03L7/099;H03L7/18 主分类号 H03L7/08
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