发明名称 Method and Layout of Semiconductor Device with Reduced Parasitics
摘要 An semiconductor device is disclosed. The device includes a semiconductor body, a layer of insulating material disposed over the semiconductor body, and a region of gate electrode material disposed over the layer of insulating material. Also included are a source region adjacent to gate region and a drain region adjacent to the gate region. A gate connection is disposed over the semiconductor body, wherein the gate connection includes a region of gate electrode material electrically coupling a contact region to the gate electrode. An insulating region is disposed on the semiconductor body beneath the gate connection.
申请公布号 US2011294273(A1) 申请公布日期 2011.12.01
申请号 US201113087102 申请日期 2011.04.14
申请人 BIRNER ALBERT;CHEN QIANG 发明人 BIRNER ALBERT;CHEN QIANG
分类号 H01L21/8234;H01L21/336 主分类号 H01L21/8234
代理机构 代理人
主权项
地址