| 摘要 |
<P>PROBLEM TO BE SOLVED: To eliminate deviation of relative position between a first conductivity region and a second trench for trench gate of a parallel pn layer. <P>SOLUTION: The method of manufacturing a super junction semiconductor device includes steps for forming, on a high concentration n-type semiconductor substrate 1, a parallel pn layer 6 where n-type semiconductor regions 5a and p-type semiconductor regions 2a are arranged in a row in the direction perpendicular to the principal surface and arranged to adjoin alternately in the parallel direction by epitaxial growth, for forming a first trench 7 in a predetermined depth at the surface layer within the n-type semiconductor region 5a of the parallel pn layer 6, and for burying a gate electrode 10 in the inside surface of an n-type thin layer 5b while interposing a gate insulating film 9 after the n-type thin layer 5b is formed on the inside surface of the trench 7. <P>COPYRIGHT: (C)2012,JPO&INPIT |
