A programmable logic device having complex logic blocks with improved logic cell functionality

摘要

A CLB-based PLD with logic cells having improved logic, register, arithmetic, logic packing and timing functions and capabilities is disclosed. The CLBs of the PLD are arranged in rows and columns of an array and are interconnect by a plurality of interconnect lines. Each of the plurality of CLBs has a first slice of logic cells and a second slice of logic cells arranged in a first column and a second column. First and second carry chains are provided between each of the logic cells of each column. At least one of the logic cells includes one or more Look Up Tables (30A,30B) for implanting logic functions on a set of inputs provided to the one logic cell and an arithmetic logic circuit (24) configured to receive a carry-in signal and to generate a carry-out signal forming part of the first carry chain. The logic cell further includes a first output register (28). The set of inputs provided to a first and a second of the Look Up Tables (30A,30B) are different, enabling a higher degree of logic efficiency or "packing" by enabling each cell to perform logic functions on two different sets of inputs as opposed to only the same set of inputs.