发明名称 Stress-managed revision of integrated circuit layouts
摘要 Roughly described, methods and systems for improving integrated circuit layouts and fabrication processes in order to better account for stress effects. Dummy features can be added to a layout either in order to improve uniformity, or to relax known undesirable stress, or to introduce known desirable stress. The dummy features can include dummy diffusion regions added to relax stress, and dummy trenches added either to relax or enhance stress. A trench can relax stress by filling it with a stress-neutral material or a tensile strained material. A trench can increase stress by filling it with a compressive strained material. Preferably dummy diffusion regions and stress relaxation trenches are disposed longitudinally to at least the channel regions of N-channel transistors, and transversely to at least the channel regions of both N-channel and P-channel transistors. Preferably stress enhancement trenches are disposed longitudinally to at least the channel regions of P-channel transistors.
申请公布号 US8069430(B2) 申请公布日期 2011.11.29
申请号 US20090546959 申请日期 2009.08.25
申请人 MOROZ VICTOR;LIN XI-WEI;PRAMANIK DIPANKAR;SYNOPSYS, INC. 发明人 MOROZ VICTOR;LIN XI-WEI;PRAMANIK DIPANKAR
分类号 G06F17/50 主分类号 G06F17/50
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