发明名称 Sense amplifier circuit and semiconductor memory device
摘要 A single-ended sense amplifier circuit amplifies a signal of a memory cell and transmitted through a bit line, and comprises first and second MOS transistors. The first MOS transistor supplies a predetermined voltage to the bit line and controls connection between the bit line and a sense node in response to a control voltage, and the second MOS transistor has a gate connected to the sense node and amplifies a signal transmitted from the bit line via the first MOS transistor. The predetermined voltage is supplied to the bit line before read operation and is set to a value such that a required voltage difference at the sense node between high and low level data of the memory cell can be obtained near a changing point between a charge transfer mode and a charge distributing mode within a range of a read voltage of the memory cell.
申请公布号 US8068369(B2) 申请公布日期 2011.11.29
申请号 US20090461858 申请日期 2009.08.26
申请人 KAJIGAYA KAZUHIKO;ELPIDA MEMORY, INC. 发明人 KAJIGAYA KAZUHIKO
分类号 G11C16/06 主分类号 G11C16/06
代理机构 代理人
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