发明名称 |
Programmable delay line compensated for process, voltage, and temperature |
摘要 |
A delay line compensated for process, voltage, and temperature variations, includes a delay locked loop (DLL) configured to delay a digital signal by the clock period of the digital signal, the DLL including a DLL delay line arranged as a plurality of cascaded sub-delay lines each sub-delay line providing one of a plurality of delay quanta in response to a digital control signal. A fractionating circuit is configured to generate a digital delay line control signal that is a fraction of the digital control signal. A digital delay line is arranged as a plurality of cascaded sub-delay lines each sub-delay line providing one of a plurality of delay quanta in response to the digital delay line control signal. |
申请公布号 |
US8067959(B2) |
申请公布日期 |
2011.11.29 |
申请号 |
US20100716469 |
申请日期 |
2010.03.03 |
申请人 |
PLANTS WILLIAM C.;ZAIN SUHAIL;LANDRY JOEL;BAKKER GREGORY W.;JASINOSKI TOMEK P.;ACTEL CORPORATION |
发明人 |
PLANTS WILLIAM C.;ZAIN SUHAIL;LANDRY JOEL;BAKKER GREGORY W.;JASINOSKI TOMEK P. |
分类号 |
H03K19/173;H03K25/00 |
主分类号 |
H03K19/173 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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