发明名称 |
Apparatus and method for implementing floating point additive and shift operations |
摘要 |
A floating point (FP) shifter for use with FP adders providing a shifted FP operand as a power of the exponent base (usually two) multiplied by a FP operand. First arithmetic processor using at least one FP shifter with FP adder. FP adder for N FP operands creating FP result, where N is at least three. Second arithmetic processor including at least one FP adder for N operands. Descriptions of FP shifter and FP adder for implementing their operational methods. Implementations of FP shifter and FP adder. |
申请公布号 |
US8069200(B2) |
申请公布日期 |
2011.11.29 |
申请号 |
US20060380613 |
申请日期 |
2006.04.27 |
申请人 |
LANDERS GEORGE;JENNINGS EARLE;QSIGMA, INC. |
发明人 |
LANDERS GEORGE;JENNINGS EARLE |
分类号 |
G06F7/38;G06F7/42;G06F7/44;H04N7/12;H04N11/02;H04N11/04 |
主分类号 |
G06F7/38 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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