发明名称 DATA LATCH CIRCUIT
摘要 A serial-format data signal is input to a data input terminal. Each of n (n represents an integer of two or more) multiple clock input terminals is configured to receive a clock signal as an input signal. An input flip-flop latches the data signal at each timing that corresponds to the corresponding clock signal. A serial/parallel converter converts the serial-format data signal into a parallel-format intermediate data signal using the corresponding clock signal. A data selector selects one from among the n intermediate data signals according to a selection signal.
申请公布号 US2011285443(A1) 申请公布日期 2011.11.24
申请号 US201113107478 申请日期 2011.05.13
申请人 SUZAWA HIDEYUKI;ADVANTEST CORPORATION 发明人 SUZAWA HIDEYUKI
分类号 H03K3/00 主分类号 H03K3/00
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