发明名称 |
LOW POWER SCAN AND DELAY TEST METHOD AND APPARATUS |
摘要 |
Scan and Scan-BIST architectures are commonly used to test digital circuitry in integrated circuits. The present disclosure improves upon low power Scan and Scan-BIST methods. The improvement allows the low power Scan and Scan-BIST architectures to achieve a delay test capability equally as effective as the delay test capabilities used in conventional scan and Scan-BIST architectures. |
申请公布号 |
US2011289371(A1) |
申请公布日期 |
2011.11.24 |
申请号 |
US201113198365 |
申请日期 |
2011.08.04 |
申请人 |
WHETSEL LEE D.;GRABER JOEL J.;TEXAS INSTRUMENTS INCORPORATED |
发明人 |
WHETSEL LEE D.;GRABER JOEL J. |
分类号 |
G01R31/3177;G01R31/317;G01R31/3185;G06F11/25 |
主分类号 |
G01R31/3177 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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