QUAD-DATA RATE CONTROLLER AND REALIZATION METHOD THEREOF

摘要

A quad-data rate (QDR) controller (100) and a realization method thereof are disclosed, in which the controller (100) includes: an arbiter (101), a control state machine (102), a reading data sampling clock generation module (103), a reading data path module (104) and a reading data path calibration module (105). The arbiter (101) arbitrates commands and data according to the state of the control state machine (102); the reading data sampling clock generation module (103) generates a homologous with frequency out-of-phase reading data sampling clock; when the control state machine (102) is "reading data path calibration state", the reading data path calibration module (105) determines the sampling clocks of a positive edge data and a negative edge data as the reading data path module (104) is reading data from the generated reading data sampling clock by reading training words; and the reading data path module (104) synchronizes the positive edge data and the negative edge data of a non-system clock domain to a system clock domain according to the determined sampling clocks. The reading delay of this technical solution is small, programmable delay devices are not needed and the technical solution is easy to implement.