PACKET PROCESSING SYSTEM ON CHIP DEVICE

摘要

The present invention relates to the area of packet processing system on chip device which that estimates the queue fill level for a particular type of data stored in the data storage device, enables sharing of the data storage unit between different units that have different traffic characteristics as per their traffic requirements and ensure that traffic from any one does not adversely impact the other, enhances the performance of the memory by modifying the memory access pattern and maintains a certain rate of reading the packet fragments from the DDR at the transmission end.