| 发明名称 |
Architecture of a nvDRAM array and its sense regime |
| 摘要 |
A process of operating a memory array includes performing all volatile and nonvolatile operations on an nvDRAM cell array via a single data interface and using only DRAM-level signals on the data interface. |
| 申请公布号 |
US8064255(B2) |
申请公布日期 |
2011.11.22 |
| 申请号 |
US20070006226 |
申请日期 |
2007.12.31 |
| 申请人 |
SCADE ANDREAS;GUENTHER STEFAN;CYPRESS SEMICONDUCTOR CORPORATION |
发明人 |
SCADE ANDREAS;GUENTHER STEFAN |
| 分类号 |
G11C14/00;G11C11/24;G11C16/06 |
主分类号 |
G11C14/00 |
| 代理机构 |
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