发明名称 Dual damascene process
摘要 Structures and methods of forming metallization layers on a semiconductor component are disclosed. The method includes etching a metal line trench using a metal line mask, and etching a via trench using a via mask after etching the metal line trench. The via trench is etched only in regions common to both the metal line mask and the via mask.
申请公布号 US8062971(B2) 申请公布日期 2011.11.22
申请号 US20080051644 申请日期 2008.03.19
申请人 RIESS PHILIPP;KALTALIOGLU ERDEM;WENDT HERMANN;INFINEON TECHNOLOGIES AG 发明人 RIESS PHILIPP;KALTALIOGLU ERDEM;WENDT HERMANN
分类号 H01L21/4763 主分类号 H01L21/4763
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