发明名称 Two-bits per cell not-and-gate (NAND) nitride trap memory
摘要 A non-volatile memory array includes a semiconductor substrate having a main surface, a first source/drain region and a second source/drain region. The second source/drain region is spaced apart from the first source/drain region. A well region is disposed in a portion of the semiconductor substrate between the first source/drain region and the second source/drain region. A plurality of memory cells are disposed on the main surface above the well region. Each memory cell includes a first oxide layer formed on the main surface of the substrate, a charge storage layer disposed above the blocking oxide layer relative to the main surface of the semiconductor substrate and second oxide layer disposed above the charge storage layer relative to the main surface of the semiconductor substrate. A plurality of wordlines are disposed above the second oxide layer relative to the main surface of the semiconductor substrate.
申请公布号 US8063428(B2) 申请公布日期 2011.11.22
申请号 US20080139429 申请日期 2008.06.13
申请人 LUNG HSIANG-LAN;MACRONIX INTERNATIONAL CO., LTD. 发明人 LUNG HSIANG-LAN
分类号 H01L29/788 主分类号 H01L29/788
代理机构 代理人
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